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30508hkim 20071127-s00004 no.a1007-1/19 ver.1.21 LC87F6D64A overview the sanyo LC87F6D64A is 8-bit microcomputer with the following on-chip functional blocks: ? cpu: operable at a minimum bus cycle time of 100ns ? 64k-byte flash rom (re-writeable on board/on-chip debugger) ? on-chip ram: 2048 byte ? vfd automatic display controller/driver ? 16-bit timer/counter (can be di vided into two 8-bit timers) ? two 8-bit timer with prescaler ? timer for use as date/time clock ? day-minute-second counter (dmsc) ? system clock divider function ? synchronous serial i/o po rt (with automatic block transmit /receive function) ? asynchronous/synchronous serial i/o port ? remote control receive function ? 8-channel 8-bit ad converter ? 14-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. features ? flash rom ? single 5v power supply, writeable on-board. ? block erase in 128 byte units ? 65536 8 bits ? ram ? 2048 9 bits ordering number : ena1007 cmos ic from 64k byte, ram 2048 byte on-chip 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F6D64A no.a1007-2/19 ? minimum bus cycle time ? 100ns (10mhz) v dd =3.0 to 5.5v ? 150ns (4mhz) v dd =2.5 to 5.5v note: the bus cycle time indicates rom read time. ? minimum instruction cycle time (tcyc) ? 300ns (10mhz) v dd =3.0 to 5.5v ? 750ns (4mhz) v dd =2.5 to 5.5v ? ports ? input/output ports data direction programmable for each bit individually: 10 (p1n, p7n) data direction programmable in nibble units: 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) ? vfd output ports large current outputs for digits: 9 (s0/t0 to s8/t8) large current outputs for digits/segments: 7 (s9/t9 to s15/t15) digit/segment outputs: 8 (s16 to s23) segment outputs: 30 (s24 to s53) ? oscillator pins: 2 (cf1/xt1, cf2/xt2) ? reset pin: 1 ( res ) ? power supply: 4 (v ss 1, v dd 1 to v dd 3) ? vfd power supply: 1 (vp) ? vfd automatic display controller ? programmable segment/digit output pattern output can be switched between digit/segment waveform output (pins 9 to 23 can be used for output of digit waveforms). parallel-drive available for large current vfd. ? 16-step dimmer function available ? timers ? timer 0: 16-bit timer/counter with capture register mode 0: 2 channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with 8- bit capture register mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register mode 3: 16-bit counter with 16-bit capture register ? timer 4: 8-bit timer with 6-bit prescaler ? timer 5: 8-bit timer with 6-bit prescaler ? base timer 1) the clock signal can be selected from any of the following. sub-clock (32.768khz crystal oscillator), system clock, and prescaler output from timer 0 2) interrupts can be selected to o ccur at one of five different times. ? day and time counter 1) using with a base timer, it can be used as 65000 day + minute + second counter. ? sio ? sio 0: 8-bit synchronous serial interface 1) lsb first /msb first function available 2) internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tcyc) 3) consecutive automatic data communication (1 to 256 bits (communication available for each b it) (stop and reopening available for each byte)) ? sio 1: 8-bit asynchronous/s ynchronous serial interface mode 0: synchronous 8-bit serial io (2-wire or 3-wire, transmit clock 2 to 512 tcyc) mode 1: asynchronous serial io (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tcyc) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tcyc) mode 3: bus mode 2 (start detection, 8 data bits, stop detection)
LC87F6D64A no.a1007-3/19 ? ad converter: 8 bits 8 channels ? remote control receiver circuit (sha ring pins with p70/int0/rmin) ? noise rejection function (units of noise rejection filter: about 120 s, when selecting a 32.768khz crystal oscillator as a clock.) ? supporting reception formats with a gu ide-pulse of half -clock/clock/none. ? determines a end of reception by detecting a no-signal periods (no carrier). (supports same reception format with a different bit length.) ? x?tal hold mode release function ? watchdog timer ? the watching timer period is set using an external rc. ? watchdog timer can produce interrupt, system reset. ? clock output function 1) able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock. 2) able to output oscillation clock of sub clock. ? interrupts: 14 sources, 10 vector interrupts ? three priority (low, high and highest) multiple inte rrupts are supported. during interrupt handling, an equal or lower priority in terrupt request is refused. ? if interrupt requests to two or more vector addresses occu r at once, the higher priority interrupt takes precedence. in the case of equal priority levels, the vect or with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/remote control receiver 4 0001bh h or l int3/base timer 0/1 5 00023h h or l t0h 6 0002bh h or l 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc 10 0004bh h or l port0/t4/t5 ? priority level: x>h>l ? for equal priority levels, vector w ith lowest address takes precedence. ? subroutine stack levels: 1024 levels maximum (stack is located in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? on-chip rc oscillation circuit for system clock use. ? on-chip cf oscillation circuit* for system clock use. (rf built in) ? on-chip crystal oscillation circuit* low speed system clock use. (rf built in) ? frequency variable rc oscillation circ uit (internal) for system clock. 1) adjustable in 4% (typ) step from a selected center frequency. 2) measures oscillation clock using a input signal from xt1 as a reference. * the cf oscillation terminal and the crystal oscillation te rminal cannot be used at th e same time because of commonness.
LC87F6D64A no.a1007-4/19 ? system clock divider function ? able to reduce current consumption available minimum instruction cycle time: 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, 76.8 s. (using 10mhz main clock) ? standby function ? halt mode halt mode is used to reduce power consumption. program execution is stopped. peripheral circuits still operate but vfd display and some serial transfer operations stop. 1) oscillation circuits are not stopped automatically. 2) release occurs on system reset or by interrupt. ? hold mode hold mode is used to reduce power consumption. both program execution and peripheral circuits are stopped. 1) the cf, rc, x?tal and frequency variable rc oscillators automatically stop operation. 2) release occurs on any of the following conditions. (1) input to the reset pin goes ?low? (2) a specified level is input to at least one of int0, int1, int2 (3) an interrupt condition arises at port 0 ? x?tal hold mode. x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits excep t the base-timer are stopped. 1) the cf, rc, frequency variable rc oscillation circuits stop automatically. 2) crystal oscillator is maintained in its state at hold mode inception. 3) release occurs on any of the following conditions. (1) input to the reset pin goes ?low? (2) setting at least one of the int0, int1 and int2 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established in the base timer circuit (5) having an interrupt source establishe d in the remote control receiver circuit ? on-chip debugger ? supports software debugging with the ic mounted on the target board. ? package form ? qfp80(14 14): lead-free type ? development tools ? on-chip debugger: tcb87- type-b + LC87F6D64A
LC87F6D64A no.a1007-5/19 package dimensions unit : mm (typ) 3255 pin assignment sanyo: qfp80(14 14) ?lead-free type? sanyo : qfp80(14x14) 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.25 0.65 (0.83) (2.7) 0.8 1 20 21 40 41 60 80 61 s37 s36 s35 s34 s33 s32 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 s17 s16 v dd 2 vp1 s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 s0/t0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 s38 s39 v dd 3 s40 s41 s42 s43 s44 s45 s46 s47 s48 s49 s50 s51 s52 s53 p10/so0 p11/si0/sb0 p12/sck0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p13/so1 p14/si1/sb1 p15/sck1 p16/int2/t0in p17/int3/t0in res v ss 1 cf1/xt1 cf2/xt2 v dd 1 p00/an0 p01/an1 p02/an2 p03/an3 p04/an4 p05/an5 p06/an6 p07/an7 p70/int0/t0lcp/rmin p71 int1/t0hcp top view LC87F6D64A
LC87F6D64A no.a1007-6/19 system block diagram alu interrupt control standby control ir pla flash rom pc bus interface port 0 port 1 sio1 timer 0 base timer vfd controller timer 4 timer 5 adc remote control receiver circuit dmsc int0 to 3 noise rejection filter acc b register c register psw rar ram stack pointer watchdog timer sio0 clock generator cf x?tal vmrc rc on-chip debugger
LC87F6D64A no.a1007-7/19 pin description pin name i/o function option v ss 1 - ? power supply (-) no v dd 1 v dd 2 v dd 3 - ? power supply (+) no vp - ? vfd power supply (-) no port0 p00 to p07 i/o ? 8bit input/output port ? data direction programmable in nibble units ? use of pull-up resistor can be specified in nibble units ? input for hold release ? input for port 0 interrupt ? other functions p04: clock output (system clock/can selected from sub clock) on-chip debugger pins: dbgp0 to dbgp2 (p05 to p07) yes port1 p10 to p17 i/o ? 8bit input/output port ? data direction programmable for each bit ? use of pull-up resistor can be specified for each bit ? other pin functions p10: sio0 data output p11: sio0 data input/bus input/output p12: sio0 clock input/output p13: sio1 data output p14: sio1 data input/bus input/output p15: sio1 clock input/output p16: int2 p17: int3/buzzer output the following types of interrupt detection are possible: rising falling rising/ falling h level l level int2 enable enable enable disable disable int3 enable enable enable disable disable yes port7 p70 to p71 ? 2bit input/output port ? data direction can be specified for each bit ? use of pull-up resistor can be specified for each bit ? other functions p70: int0 input/hold release input/timer 0l capture input/ output for watchdog timer/remote control receiver input p71: int1 input/hold release input/timer 0h capture input the following types of interrupt detection are possible: rising falling rising/ falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable s0/t0 to s8/t8 o ? large current output for vfd display controller digit (can be used for segment) no s9/t9 to s15/t15 o ? large current output for vfd display controller segment/digit no s16 to s53 o ? output for vfd display controller segment no res i reset terminal no cf1/xt1 i ? input terminal for ceramic oscillator < crystal oscillator selected> ? input for 32.768khz crystal oscillation when not in use, connect to v dd 1. no cf2/xt2 o ? output terminal for ceramic oscillator < crystal oscillator selected> ? output for 32.768khz crystal oscillation when not in use, set to oscillation mode and leave open circuit. no
LC87F6D64A no.a1007-8/19 port output types output configuration and pull-up/pull-down resist or options are shown in the following table. input/output is possible even when port is set to output mode. terminal option selected in units of options output format pull-up resistor pull-down resistor 1 cmos programmable - p00 to p07 (note 1) each bit 2 nch-open drain programmable - 1 cmos programmable - p10 to p17 each bit 2 nch-open drain programmable - p70 - none nch-open drain programmable - p71 - none cmos programmable - s0/t0 to s15/t15 s16 to s53 - none high voltage pch-open drain - fixed note 1: programmable pull-up resisters of port 0 can be attached in nibble units (p00 to p03, p04 to p07). * note: connect as follows to reduce noise on v dd and increase the back-up time. v ss 1 must be connected together and grounded. power supply lsi v dd 1 back-u p ca p acitors v dd 2 v dd 3 v ss 1 vfd powers
LC87F6D64A no.a1007-9/19 absolute maximum ratings at ta = 25c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 v i (1) cf1/xt1, res -0.3 v dd +0.3 input voltage v i (2) vp v dd -45 v dd +0.3 v o (1) s0/t0 to s15/t15 s16 to s53 v dd -45 v dd +0.3 output voltage v o (2) cf2/xt2 -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 7 -0.3 v dd +0.3 v ioph(1) ports 0, 1 ? cm os output selected ? current at each pin -10 ioph(2) port 71 current at each pin -5 ioph(3) s0/t0 to s15/t15 current at each pin -30 peak output current ioph(4) s16 to s53 current at each pin -15 iomh(1) ports 0, 1 ? cm os output selected ? current at each pin -7.5 iomh(2) port 71 current at each pin -3 iomh(3) s0/t0 to s15/t15 current at each pin -15 average output current iomh(4) s16 to s53 current at each pin -10 ioah(1) port 0 total of all pins -30 ioah(2) port 1 total of all pins -30 ioah(3) ports 0, 1 total of all pins -30 ioah(4) port 71 total of all pins -5 ioah(5) s0/t0 to s15/t15 total of all pins -60 ioah(6) s16 to s33 total of all pins -60 ioah(7) s0/t0 to s15/t15 s16 to s33 total of all pins -60 ioah(8) s34 to s39 total of all pins -60 ioah(9) s40 to s47 total of all pins -60 ioah(10) s48 to s53 total of all pins -60 high level output current total output current ioah(11) s34 to s53 total of all pins -60 iopl(1) ports 0, 1 current at each pin 20 peak output current iopl(2) port 7 current at each pin 10 ipml(1) ports 0, 1 current at each pin 15 total output current ioml(2) port 7 current at each pin 7.5 ioal(1) port 0 total of all pins 50 ioal(2) port 1 total of all pins 50 ioal(3) port 7 total of all pins 20 low level output current total output current ioal(4) ports 0, 1, 7 total of all pins 80 ma maximum power dissipation pd max qfp80(14 14) ta=-40 to +85 c mw operating temperature range topr -40 +85 storage temperature range tstg -55 +125 c
LC87F6D64A no.a1007-10/19 allowable operating conditions at ta = -40c to +85c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit v dd (1) 0.300 s tcyc 200 s 3.0 5.5 operating supply voltage range (note 2-1) v dd (2) v dd 1=v dd 2=v dd 3 0.735 s tcyc 200 s 2.5 5.5 hold voltage vhd v dd 1 ram and the register data are kept in hold mode. 2.0 5.5 pull-down supply voltage vp vp -35 v dd v ih (1) ports 0, 1 output disable 2.5 to 5.5 0.3v dd +0.7 v dd v ih (2) port 70 watchdog timer output disable 2.5 to 5.5 0.9v dd v dd input high voltage v ih (3) xt1/cf1, res 2.5 to 5.5 0.75v dd v dd v il (1) ports 0, 1 port 71 port 70 port input/interrupt output disable 2.5 to 5.5 v ss 0.1v dd +0.4 v il (2) port 70 watchdog timer output disable 2.5 to 5.5 v ss 0.8v dd -1.0 input low voltage v il (3) xt1/cf1, res 2.5 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.300 200 operation cycle time tcyc 2.5 to 5.5 0.735 200 s 3.0 to 5.5 0.1 10 ? cf2 open circuit ? system clock divider set to 1/1 ? external clock duty=50 5% 2.5 to 5.5 0.1 4 3.0 to 5.5 0.2 20 external system clock frequency fexcf(1) cf1 ? cf2 open circuit ? system clock divider set to 1/2 ? external clock duty=50 5% 2.5 to 5.5 0.2 8 mhz fmcf(1) cf1, cf2 ? 10mhz ceramic resonator oscillation ? refer to figure 1 3.0 to 5.5 10 fmcf(2) cf1, cf2 ? 4mhz ceramic resonator oscillation ? refer to figure 1 2.5 to 5.5 4 fmrc rc oscillation 2.5 to 5.5 0.3 1.0 2.0 fmvmrc frequency variable rc oscillation circuit 2.5 to 5.5 4 mhz oscillation stabilizing time period (note 2-2) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 2.5 to 5.5 32.768 khz note 2-1: re-writeable on board v dd 4.5v. note 2-2: the oscillation constant is shown in table 1 and table 2. the cf oscillation terminal and the crystal oscillation terminal cannot be used at the same time because of commonness.
LC87F6D64A no.a1007-11/19 electrical characteristics at ta = -40c to +85c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 7 ? output disable ? pull-up resister off. ? v in =v dd (including off state leak current of the output tr.) 2.5 to 5.5 1 i ih (2) res v in =v dd 2.5 to 5.5 1 input high current i ih (3) cf1/xt1 v in =v dd 2.5 to 5.5 1 i il (1) ports 0, 1, 7 ? output disable ? pull-up resister off. ? v in =v ss (including off state leak current of the output tr.) 2.5 to 5.5 -1 i il (2) res v in =v ss 2.5 to 5.5 -1 input low current i il (3) cf1/xt1 v in =v ss 2.5 to 5.5 -1 a v oh (1) i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.5ma 3.0 to 5.5 v dd -1 v oh (3) port 0: cmos output option ports 1 i oh =-0.1ma 2.5 to 5.5 v dd -0.5 v oh (4) port 71 i oh =-0.4ma 2.5 to 5.5 v dd -1 v oh (5) i oh =-20.0ma 4.5 to 5.5 v dd -1.8 v oh (6) i oh =-10.0ma 3.0 to 5.5 v dd -1.8 v oh (7) s0/t0 to s15/t15 ? i oh =-1.0ma ? i oh at any single pin is not over 1ma. 2.5 to 5.5 v dd -1 v oh (8) i oh =-5.0ma 4.5 to 5.5 v dd -1.8 v oh (9) i oh =-2.5ma 3.0 to 5.5 v dd -1.8 output high voltage v oh (10) s16 to s53 ? i oh =-1.0ma ? i oh at any single pin is not over 1ma. 2.5 to 5.5 v dd -1 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =5ma 3.0 to 5.5 1.5 v ol (3) ports 0, 1 i ol =1.6ma 2.5 to 5.5 0.4 output low voltage v ol (4) port 7 i ol =1ma 2.5 to 5.5 0.4 v 4.5 to 5.5 15 40 70 pull-up resistor rpu ports 0, 1, 7 v oh =0.9v dd 2.5 to 4.5 25 70 150 k ioff(1) ? output p-ch tr. off ? v out =v ss 2.5 to 5.5 -1 output off-leak current ioff(2) s0/t0 to s15/t15, s16 to s53 ? output p-ch tr. off ? v out =v dd -40v 2.5 to 5.5 -30 a pull-down resistor rpd ? s0/t0 to s15/t15 ? s16 to s53 ? output p-ch tr. off ? v out =3v ? vp=-30v 5.0 60 100 200 k hysteresis voltage vhys(1) ? ports 0, 1, 7 ? res 2.5 to 5.5 0.1v dd v pin capacitance cp all pins ? f=1mhz ? all other terminals connected to v ss . ? ta=25 c 2.5 to 5.5 10 pf
LC87F6D64A no.a1007-12/19 serial i/o characteristics at ta = -40c to +85c, v ss 1 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 input clock high level pulse width tsckha(1) sck0(p12) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 2.5 to 5.5 4 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 6. 1/2 tsck serial clock output clock high level pulse width tsckha(2) sck0(p12) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. 2.5 to 5.5 tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc data setup time tsdi(1) 2.5 to 5.5 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.5 to 5.5 0.03 tdd0(1) ? continuous data transmission/reception mode ? (note 4-1-3) 2.5 to 5.5 (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.5 to 5.5 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.5 to 5.5 (1/3)tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
LC87F6D64A no.a1007-13/19 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 6. 2.5 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.5 to 5.5 1/2 tsck data setup time tsdi(2) 2.5 to 5.5 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.5 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.5 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -40c to +85c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p16) ? interrupt acceptable ? events to timer 0, 1 can be input. 2.5 to 5.5 1 tpih(2) tpil(2) int3(p17) (noise rejection ratio set to 1/1.) ? interrupt acceptable ? events to timer 0 can be input. 2.5 to 5.5 2 tpih(3) tpil(3) int3(p17) (noise rejection ratio set to 1/32.) ? interrupt acceptable ? events to timer 0 can be input. 2.5 to 5.5 64 tpih(4) tpil(4) int3(p17) (noise rejection ratio set to 1/128.) ? interrupt acceptable ? events to timer 0 can be input. 2.5 to 5.5 256 tcyc high/low level pulse width tpil(5) res reset possible 2.5 to 5.5 200 s
LC87F6D64A no.a1007-14/19 ad converter characteristics at ta = -40c to +85c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute precision et (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 15.62 (tcyc= 0.488 s) 97.92 (tcyc= 3.06 s) ad conversion time=32 tcyc (adcr2=0) (note 6-2) 3.0 to 5.5 23.52 (tcyc= 0.735 s) 97.92 (tcyc= 3.06 s) 4.5 to 5.5 18.82 (tcyc= 0.294 s) 97.92 (tcyc= 1.53 s) conversion time tcad ad conversion time=64 tcyc (adcr2=1) (note 6-2) 3.0 to 5.5 47.04 (tcyc= 0.735 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07) vain=v ss 3.0 to 5.5 -1 a note 6-1: absolute precision not including quantizing error ( 1/2 lsb). note 6-2: conversion time means time fro m executing ad conversion instruction to loading complete digital value to register. consumption current characteristics at ta = -40c to +85c, v ss 1 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 4.5 to 5.5 8.0 24 iddop(1) ? fmcf=10hz for ceramic resonator oscillation ? system clock: 10mhz ? internal rc oscillation stopped. ? 1/1 frequency division ratio 3.0 to 4.5 6.1 19 4.5 to 5.5 10.5 32 iddop(2) ? cf1=15mhz for external clock ? system clock: cf1 oscillation ? internal rc oscillation stopped. ? 1/2 frequency division ratio 3.0 to 4.5 9.5 28 4.5 to 5.5 3.8 9.5 iddop(3) ? fmcf=4mhz for ceramic resonator oscillation ? system clock: 4mhz ? internal rc oscillation stopped. ? 1/1 frequency division ratio 3.0 to 4.5 3.1 7.8 4.5 to 5.5 0.72 3 iddop(4) ? fmcf=0hz (no oscillation) ? system clock: rc oscillation ? divider set to 1/2 2.5 to 4.5 0.53 2 ma 4.5 to 5.5 39 220 current dissipation during basic operation (note 7-1) iddop(5) v dd 1 =v dd 2 =v dd 3 ? fsx?tal=32.768khz for crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? 1/2 frequency division ratio 2.5 to 4.5 25 150 a note 7-1: the currents of the output transistors and the pull-up mos transistors are ignored. continued on next page.
LC87F6D64A no.a1007-15/19 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 4.5 to 5.5 3.0 9 iddhalt(1) halt mode ? fmcf=10mhz for ceramic resonator oscillation ? system clock : 10mhz ? internal rc oscillation stopped. ? divider: 1/1 3.0 to 4.5 2.1 6.3 4.5 to 5.5 4.2 12.5 iddhalt(2) halt mode ? cf1=15mhz for external clock ? system clock : cf1 oscillation ? internal rc oscillation stopped. ? divider 1/2 3.0 to 4.5 2.5 7.8 4.5 to 5.5 1.4 3.5 iddhalt(3) halt mode ? fmcf=4mhz for ceramic resonator oscillation ? system clock : 4mhz ? internal rc oscillation stopped. ? divider: 1/1 2.5 to 4.5 1.0 2.5 ma 4.5 to 5.5 420 1600 iddhalt(4) halt mode ? fmcf=0hz (when os cillation stops.) ? system clock : rc oscillation ? divider: 1/2 2.5 to 4.5 280 1100 4.5 to 5.5 24 80 current dissipation halt mode (note 7-1) iddhalt(5) v dd 1 =v dd 2 =v dd 3 halt mode ? fsx?tal=32.768khz for crystal oscillation ? internal rc oscillation stopped. ? system clock : 32.768khz ? divider: 1/2 2.5 to 4.5 14 60 4.5 to 5.5 0.10 20 current dissipation hold mode iddhold(1) v dd 1 hold mode ? cf1=v dd or open circuit (when using external clock) 2.5 to 4.5 0.02 15 4.5 to 5.5 21 65 current dissipation date/time clock hold mode iddhold(2) v dd 1 date/time clock hold mode ? cf1=v dd or open circuit (when using external clock) ? fsx?tal=32.768khz for crystal oscillation 2.5 to 4.5 11 50 a note 7-1: the currents of the output transistors and the pull-up mos transistors are ignored. f-rom programming characteristics at ta = +10c to +55c, v ss 1 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit on-board writing current iddfw(1) v dd 1 ? the current dissipation of the microcomputer is excluded. 4.5 to 5.5 5 10 ma tfw(1) ? erase time 20 30 ms writing time tfw(2) ? writing time 4.5 to 5.5 40 60 s
LC87F6D64A no.a1007-16/19 characteristics of a sample main system clock oscillation circuit the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 [pf] c2 [pf] rd1 [ ] operating supply voltage range [v] typ [ms] max [ms] notes cstce10m0g52-r0 10 10 1k 2.8 to 5.5 0.029 10mhz murata cstls10m0g53-b0 15 15 1k 3.0 to 5.5 0.028 cstcr4m00g53-r0 15 15 2.2k 2.3 to 5.5 0.034 4mhz murata cstls4m00g53-b0 15 15 2.2k 2.3 to 5.5 0.030 the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (refer to figure 4) characteristics of a sample subs ystem clock oscillator circuit the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer table 2 characteristics of a sample subsystem clock oscillator circuit with a crystal oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 [pf] c4 [pf] rf [ ] rd2 [ ] operating supply voltage range [v] typ [s] max [s] notes the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after rel easing the hold mode. (refer to figure 4) notes: since the circuit pattern affects the oscillation frequ ency, place the oscillation-relate d parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing measurement point 0.5v dd rf2 rd2 xt1 xt2 c4 x?tal c3 rf1 rd1 cf1 cf2 c2 cf c1
LC87F6D64A no.a1007-17/19 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization time power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unfixed reset instruction execution v dd v dd limit 0v internal rc oscillation cf1,cf2 xt1, xt2 operating mode hold release signal hold reset signal valid tmscf tmsx?tal hold halt witout hold release signal
LC87F6D64A no.a1007-18/19 figure 5 reset circuit figure 6 serial i/o waveform figure 7 pulse input timing signal waveform tpil tpih c res v dd r res res note: set c res , r res values such that reset time exceeds 200 s. data ram transmission period (only sio0) data ram transmission period (only sio0) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo
LC87F6D64A no.a1007-19/19 ps this catalog provides information as of december, 2007. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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